High voltage MOS devices and methods of forming MOS devices

ABSTRACT

A P channel high voltage metal oxide semiconductor device is described which is integrated in the same chip or wafer as standard P channel and N channel metal oxide semiconductor devices. The high voltage device has a lightly doped p −  drift region adjacent to the heavily doped p +  drain region. A high voltage support region is formed directly below the drift region using high energy ion implantation with an implantation energy of between about 2 and 3 Mev. This high energy ion implantation is used to precisely locate the high voltage support region directly below the drift region. This high voltage support region avoids punch-through from the P channel drain through the drift region into the substrate while using a standard depth for the n type well. This allows the high voltage device to be integrated into the same chip or wafer as standard P channel and N channel metal oxide semiconductor devices.

BACKGROUND OF THE INVENTION

[0001] (1) Field of the Invention

[0002] This invention relates to high voltage MOS, metal oxidesemiconductor, devices and methods of forming MOS devices, and moreparticularly to high voltage MOS devices which do not require a deep ntype silicon well or p type silicon well.

[0003] (2) Field of the Invention

[0004] It is frequently desirable to fabricate high voltage metal oxidesemiconductor, MOS, devices. These devices typically use lightly dopeddrift regions adjacent to more heavily doped drain regions to suppressthe onset of avalanche multiplication. These devices also typically usean n well or p well having increased depth.

[0005] U.S. Pat. No. 4,232,327 to Hsu and U.S. Pat. No. 5,512,495 to Meiet al. describes high voltage MOSFETS, metal oxide semiconductor fieldeffect transistors, using a lightly doped drift region adjacent to amore heavily doped drain.

[0006] U.S. Pat. No. 6,133,107 to Menegoli and U.S. Pat. No. 5,591,675to Fujishima et al. describe high voltage MOSFETs using deep wellregions.

SUMMARY OF THE INVENTION

[0007] It is frequently desirable to form standard voltage N channel orP channel metal oxide semiconductor and high voltage N channel metaloxide semiconductor devices on the same chip or wafer. This is notpossible if the high voltage P channel device requires a deep n well.FIG. 1 shows a cross section view of a high voltage P channel device. Alightly doped epitaxial layer 12 of p⁻ type silicon is formed over asubstrate 10 of heavily doped p⁺ type silicon. The lightly doped well 13of n⁻ type silicon, in which the high voltage device is formed, has adepth 28 larger than that for a typical device. This results in asmaller gap 30 between the bottom of the well 13 and the substrate 10.The typical high voltage device shown in FIG. 1 has a p⁺ type source 16on one side of the channel, a p⁻ type drift region 20 on the other sideof the channel, and a p⁺ type drain adjacent to the drift region 20. Thedevice shown in FIG. 1 also has a thick oxide 22A overlaying the driftregion 20, thick oxide isolation regions 22B, a gate oxide layer 26, anda gate electrode 24.

[0008] The depth 28 of the well is a critical factor in determining theoperating voltage of the high voltage P channel device. If the well 13is too deep the well to substrate gap 30 will be too small which willreduce the maximum operating voltage available. If the well 13 is tooshallow punch-through from the P channel drain 18 through the driftregion 20 into the substrate 10 will occur. The formation of a deep wellof n type silicon is typically formed using a Phosphorous implantfollowed by a long thermal drive in. This thermal drive in has theundesirable effect of enhancing diffusion of impurities from the p⁺substrate 10 into the p⁻ epitaxial layer. This requires a thicker p⁻epitaxial layer which will degrade the latch-up immunity of standardCMOS devices, causing problems for integrating high voltage devices andstandard devices in the same chip or wafer.

[0009] It is a principle objective of this invention to provide a methodof forming high voltage metal oxide semiconductor P channel deviceswithout increasing the depth of the well of n type silicon in which thehigh voltage devices are located and which can be integrated on the samechip or wafer with standard metal oxide semiconductor devices.

[0010] It is another principle objective of this invention to providehigh voltage metal oxide semiconductor P channel devices having astandard depth of the well of n type silicon in which the high voltagedevices are located and which can be integrated on the same chip orwafer with standard metal oxide semiconductor devices.

[0011] These objectives are achieved by implanting a high voltagesupport region 44, see FIG. 2, directly below the drift region 20. Thehigh voltage support region is doped to be heavily doped n type silicon,n+ type silicon. A higher energy implanter than that used in formingother doped regions is used to locate the high voltage support regiondirectly below the drift region 20. This high voltage support regionavoids punch-through from the P channel drain 18 through the driftregion 20 into the substrate 10 while using a standard depth for the ntype well 14, see FIG. 2.

BRIEF DESCRIPTION OF THE DRAWINGS

[0012]FIG. 1 shows a cross section view of a standard P channel highvoltage metal oxide semiconductor device having a deep n well.

[0013]FIG. 2 shows a cross section view of a P channel high voltagemetal oxide semiconductor device of this invention having an ionimplanted high voltage support region and an n well of standard depth.

[0014]FIG. 3 shows a cross section view of the formation of an n⁻ typewell of standard depth, in a p⁻ epitaxial region formed on a p⁺ typesubstrate, using ion implantation.

[0015]FIG. 4. shows a cross section view of the formation of a p⁻ typeregion which will form the drain drift region, along with the formationof the underlying high voltage support region.

[0016]FIG. 5A shows a cross section view of the mask used to grow thethick oxide regions.

[0017]FIG. 5B shows a cross section view of the thin and thick oxideregions after removal of the mask.

[0018]FIG. 6 shows a cross section view of the formation of the sourceand drain regions.

[0019]FIG. 7 shows a cross section view of the formation of a second ntype well, in the same chip or wafer as the as the high voltage device,in which a standard P channel device will be formed.

[0020]FIG. 8 shows a cross section view of a standard P channel deviceformed in the second n type well of FIG. 7.

[0021]FIG. 9 shows a cross section view of a standard N channel deviceformed in the same chip or wafer as the high voltage device.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0022] Refer to FIG. 2 for a detailed description of the high voltagemetal oxide semiconductor device of this invention. FIG. 2 shows a crosssection view of the high voltage, P channel, metal oxide semiconductordevice of this invention. The device is formed on a heavily doped p⁺type substrate 10 having an impurity density of between about 5×10¹⁹ and1.3×10²⁰ atoms/cm³. A lightly doped p⁻ type epitaxial layer 12, havingan impurity density of between about 1×10¹⁵ and 3×10¹⁵ atoms/cm³, isformed on the substrate 10. A lightly doped n⁻ type well 14, having animpurity density of between about 1×10¹⁶ and 4×10¹⁶ atoms/cm³ and astandard well depth 29 of between about 4 and 6 microns, is formed inthe epitaxial layer 12. There is a standard gap 31 between the bottom ofthe n⁻ type well 14 and the substrate 10. Heavily doped p⁺ type source16 and drain 18 regions, having an impurity density of between about5×10¹⁹ and 2×10²⁰ atoms/cm³ are formed in the n⁻ type well 14. A lightlydoped p⁻ type drift region 17, having an impurity density of betweenabout 3×10¹⁶ and 7×10¹⁶ atoms/cm³, is formed in the n⁻ type well 14adjacent to the drain 18. A thick oxide layer 22, thermally grown fieldsilicon oxide, is formed over the drift region 20. A gate electrode 24and gate oxide 26, silicon oxide, are formed over the channel region 11.The key part of the device of this invention is a n⁻ doped high voltagesupport region 44 formed directly under the drift region 17. The highvoltage support region 44 has an impurity density of between about5×10¹⁵ and 2×10¹⁶ atoms/cm³. The channel region 11 is between the source16 and the drift region 17. The device shown in FIG. 2 and describedherein can operate at voltages up to about 35 volts between the source16 and drain 18.

[0023] Refer now to FIGS. 2-9 for a detailed description of thepreferred method of forming the P channel high voltage metal oxidesemiconductor device of this invention. FIG. 3 shows a lightly doped p⁻type epitaxial layer 12, having an impurity density of between about1×10¹⁵ and 3×10¹⁵ atoms/cm³, formed on a heavily doped p⁺ type substrate10 having an impurity density of between about 5×10¹⁹ and 1.3×10²⁰atoms/cm³. A first resist mask 31 is formed over the epitaxial layer andan ion beam 29 implants a beam of phosphorous ions into the epitaxiallayer 12, using an implantation energy of between about 120 and 180 kev,to form a lightly doped n⁻ type well 14 with an impurity concentrationof between about 1×10¹⁶ and 4×10¹⁶ atoms/cm³. The first resist mask 72is formed using photoresist and standard photolithographic techniques.The first resist mask is then removed and the well 14 is driven in suchthat the final well depth 29 is between about 4 and 6 microns.

[0024] As shown in FIG. 4, a second resist mask 32 is then formed havingan opening at the location of the drain and drift regions. A lightlydoped p⁻ region 17 is then formed using ion implantation wherein the ionimplantation beam 34 is a beam of boron ions, thereby forming a lightlydoped p⁻ region 17 having an impurity concentration of between about3×10¹⁶ and 7×10¹⁶ atoms/cm³. The ion implantation energy of the boronions can be, for example, between about 270 and 330 kev. This lightlydoped p⁻ region 17 will become the drift region. The second resist mask32 is formed using photoresist and standard photolithographictechniques.

[0025] Referring again to FIG. 4, the next step is the key step of theinvention wherein a high voltage support region 44 is formed. This stepuses ion implantation wherein the ion implantation beam 34 is a beam ofphosphorous. This ion implantation step uses an implantation energy ofbetween about 2 and 3 Mev. This implantation energy allows the highvoltage support region 44 to be precisely located directly under thedrift region 17. The high voltage support region 44 has an impurityconcentration of between about 5×10¹⁵ and 2×10¹⁶ atoms/cm³.

[0026] As shown in FIGS. 5A the second resist mask is removed and athird resist mask 36 is then formed having openings for thick oxideregions. The third resist mask 36 is formed using photoresist andstandard photolithographic techniques. As shown in FIG. 5B, thick oxideregions 22A and 22B are then formed using conventional LOCOS techniques.The third resist mask is thin removed. The thick oxide regionsidentified by reference number 22B are used to isolate the adjacenttransistors. The thick oxide region identified by reference number 22Ais used to reduce the electric field in this region.

[0027] Next, as shown in FIG. 6, the gate oxide 26A and gate electrode24 are formed using conventional methods. A fourth resist mask 42 isthen formed using photoresist and standard photolithographic methods.The fourth resist mask 42 has an opening directly over the transistor.Heavily doped p⁺ source 16 and drain 18 regions art then formed usingion implantation wherein the ion implantation beam 38 is a beam of BF₂ions implanted with an implantation energy of between about 60 and 80kev, leaving a lightly doped drift region 17 having an impurityconcentration of between about 3×10¹⁶ and 7×10¹⁶ atoms/cm³. The source16 and drain 18 regions have an impurity concentration of between about5×10¹⁹ and 2×10²⁰ atoms/cm³. The channel region 11 is between the sourceregion 16 and the drift region 17.

[0028] The fourth resist mask 42 is then removed resulting in thecompleted high voltage device shown in FIG. 2. The device shown in FIG.2 and described herein can operate at voltages up to about 35 voltsbetween the source 16 and drain 18.

[0029] The high voltage device shown in FIG. 2 can be integrated withstandard devices on the same chip or wafer. FIG. 7 shows additionalopenings in the first resist mask 72 to form a second n⁻ well 50 in theepitaxial layer using implantation of the same beam of phosphorous ions70 used to form the well in which the high voltage device is formed.This is the same implantation as used to form the well in which the highvoltage device is formed and uses an implantation energy of betweenabout 120 and 180 kev, to form a lightly doped second n⁻ type well 50with an impurity concentration of between about 1×10¹⁶ and 4×10¹⁶atoms/cm³, which is the same as the well in which the high voltagedevice is formed. As shown in FIG. 8, standard p type source 52 anddrain 54 regions are formed defining a channel region 51. A gateelectrode 58 and gate oxide 56, silicon oxide, are formed over thechannel region 51. This standard P channel device is integrated in thesame chip or wafer as the previously described high voltage device.

[0030] As shown in FIG. 9, standard n type source 60 and drain 62regions are formed in the lightly doped epitaxial region 12 defining achannel region 61. A gate electrode 66 and gate oxide 64, silicon oxide,are formed over the channel region 61. This standard N channel device isintegrated in the same chip or wafer as the previously described highvoltage device and the previously described standard P channel device.

[0031] While the invention has been particularly shown and describedwith reference to the preferred embodiments thereof, it will beunderstood by those skilled in the art that various changes in form anddetails may be made without departing from the spirit and scope of theinvention.

What is claimed is:
 1. A method of forming high voltage metal oxidesemiconductor devices, comprising: providing a substrate of p typesilicon having between about 5×10¹⁹ and 5×10²⁰ impurity atoms/cm³;forming an epitaxial layer of p type silicon having between about 1×10¹⁵and 3×10¹⁵ impurity atoms/cm³ on said substrate; forming a first well ofn type silicon having between about 1×10¹⁶ and 4×10¹⁶ impurity atoms/cm³in said epitaxial layer using a first ion implantation and a firstresist mask, wherein said first well has a first channel region and saidfirst channel region has a first edge and a second edge; forming a driftregion of p type silicon having between about 3×10¹⁶ and 7×10¹⁶ impurityatoms/cm³ in said first well using a second ion implantation and asecond resist mask, wherein said drift region is adjacent to said secondedge of said first channel region; forming a high voltage support regionof n⁻ type silicon having between about 5×10¹⁵ and 2×10¹⁶ impurityatoms/cm³ in said first well directly below said drift region using athird ion implantation and said second resist mask; forming a thickoxide over said drift region using a third resist mask; forming a firstgate oxide and a first gate electrode over said first channel region;and forming a first source and a first drain of p type silicon havingbetween about 5×10¹⁹ and 2×10²⁰ impurity atoms/cm³ in said first wellusing a fourth ion implantation and a fourth resist mask, wherein saidfirst drain is adjacent to said drift region and said drift region isbetween said first drain and said second edge of said first channelregion.
 2. The method of claim 1 wherein said first resist mask, saidsecond resist mask, said third resist mask, and said fourth resist maskare formed using photoresist and photolithographic processing.
 3. Themethod of claim 1 wherein said first ion implantation uses implantationof phosphorous ions with an ion implantation energy of between about 120and 180 kev.
 4. The method of claim 1 wherein said second ionimplantation uses implantation of boron ions with an ion implantationenergy of between about 270 and 330 kev.
 5. The method of claim 1wherein said third ion implantation uses implantation of phosphorousions with an ion implantation energy of between about 2 and 3 Mev. 6.The method of claim 1 wherein said fourth ion implantation usesimplantation of BF₂ ions with an ion implantation energy of betweenabout 60 and 80 kev.
 7. The method of claim 1 wherein said thick oxideis thermally grown silicon oxide.
 8. The method of claim 1 wherein saidfirst gate oxide is a thermally grown silicon oxide.
 9. The method ofclaim 1 wherein the operating voltage between said first source and saidfirst drain is 35 volts or less.
 10. The method of claim 1, furthercomprising: forming a second well of n type silicon having between about1×10¹⁶ and 4×10¹⁶ impurity atoms/cm³ in said epitaxial layer outside ofsaid first well using said first ion implantation and said first resistmask, wherein said second well has a second channel region; forming asecond gate electrode and a second gate oxide over said second channelregion; and forming a second source and second drain of p type siliconin said second well, wherein said second channel region is between saidsecond source and said second drain.
 11. The method of claim 1, furthercomprising: forming a third source and a third drain of n type siliconin said epitaxial layer outside of said first well, thereby defining athird channel region in said epitaxial layer outside of said first welland between said third source and said third drain; and forming a thirdgate electrode and a third gate oxide over said third channel region.12. A high voltage metal oxide semiconductor device, comprising: asubstrate of p type silicon having between about 5×10¹⁹ and 1.3×10²⁰impurity atoms/cm³; an epitaxial layer of p type silicon having betweenabout 1×10¹⁵ and 3×10¹⁵ impurity atoms/cm³ formed on said substrate; afirst well, having a first channel region, formed within said epitaxiallayer wherein said first well is n type silicon having between about1×10¹⁶ and 4×10¹⁶ impurity atoms/cm³ and said first channel region has afirst edge and a second edge; a drift region formed in said first welladjacent to said second edge of said first channel region wherein saiddrift region is p type silicon having between about 3×10¹⁶ and 7×10¹⁶impurity atoms/cm³; a high voltage support region formed in said firstwell directly below said drift region wherein said high voltage supportregion is n type silicon having between about 5×10¹⁵ and 2×10¹⁶ impurityatoms/cm³; a thick oxide formed directly above said drift region; afirst gate formed on a first gate oxide above said first well anddirectly above said first channel region; a first source formed in saidfirst well adjacent to said first edge of said first channel regionwherein said first source is p type silicon having between about 5×10¹⁵and 2×10¹⁶ impurity atoms/cm³; and a first drain formed in said firstwell adjacent to said drift region so that said drift region is betweensaid first channel region and said first drain wherein said first drainis p type silicon having between about 5×10¹⁹ and 2×10²⁰ impurityatoms/cm³.
 13. The high voltage metal oxide semiconductor device ofclaim 12 wherein said high voltage support region is formed using ionimplantation of phosphorous ions using an ion implantation energy ofbetween about 2 and 3 Mev, thereby enabling said high voltage supportregion to be located directly below said drift region.
 14. The highvoltage metal oxide semiconductor device of claim 12 wherein said thickoxide is a silicon oxide.
 15. The high voltage metal oxide semiconductordevice of claim 12 wherein said first gate oxide is a silicon oxide. 16.The high voltage metal oxide semiconductor device of claim 12 whereinsaid first gate extends from said first edge of said first channelregion to said second edge of said second channel region.
 17. The highvoltage metal oxide semiconductor device of claim 12 wherein theoperating voltage between said first source and said first drain is 35volts or less.
 18. The high voltage metal oxide semiconductor device ofclaim 12, further comprising: a second well of n type silicon havingbetween about 1×10¹⁶ and 4×10¹⁶ impurity atoms/cm³ formed in saidepitaxial layer outside of said first well; a second source of p typesilicon formed in said second well; a second drain of p type siliconformed in said second well, thereby defining a second channel region insaid second well between said second source and said second drain; and asecond gate electrode and a second gate oxide formed over said secondchannel region.
 19. The high voltage metal oxide semiconductor device ofclaim 12, further comprising: a third source of n type silicon formed insaid epitaxial layer outside of said first well; a third drain of n typesilicon formed in said epitaxial layer outside of said first well,thereby defining a third channel region in said epitaxial layer outsideof said first well and between said third source and said third drain;and a third gate electrode and a third gate oxide formed over said thirdchannel region.